NXP Semiconductors /QN908XC /USART0 /FIFOINTENCLR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as FIFOINTENCLR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TXERR)TXERR 0 (RXERR)RXERR 0 (TXLVL)TXLVL 0 (RXLVL)RXLVL

Description

FIFO interrupt enable clear (disable) and read register.

Fields

TXERR

Writing one clears the corresponding bits in the FIFOINTENSET register.

RXERR

Writing one clears the corresponding bits in the FIFOINTENSET register.

TXLVL

Writing one clears the corresponding bits in the FIFOINTENSET register.

RXLVL

Writing one clears the corresponding bits in the FIFOINTENSET register.

Links

()